1. Field of the Invention
The present invention relates to a high voltage device with electrostatic discharge (ESD) protection and more particularly to high voltage device with a parasitic silicon controlled rectifier (SCR) which has a shorter discharge path.
2. Description of the Related Art
As semiconductor manufacturing evolves, ESD protection has become one of the most critical reliability issues for integrated circuits (IC). Several ESD test modes, such as machine mode (MM) or human body mode (HBM), have been proposed to imitate the circumstances under which an ESD event occurs. The ability to withstand certain levels of ESD is successful commercialization essential for an IC.
ESD protection circuits are generally located at input/output ports or between power rails, to release electrostatic stress before the electrostatic stress damages interior or core electronic circuits in an IC. ESD protection circuits are typically designed to be switched off during common/normal signal operation and switched on during an ESD event to release accumulated electrostatic charge.
Among ESD protection circuits, silicon controlled rectifiers (SCR) have been recognized as an effective ESD protection device. FIG. 1 shows characteristic curves of a silicon controlled rectifier (SCR). Due to the low holding voltage (Vhold, about 1V in a CMOS process) of the SCR, power (Power=IESD×Vhold) generated by the SCR device during ESD stress is lower than other ESD protection devices (such as diode, MOS, BJT, or field-oxide device) in CMOS technologies. Therefore, the SCR device can sustain much higher ESD stress within a smaller layout area in the CMOS IC.
FIG. 2 shows a conventional high voltage device with a parasitic SCR as ESD protection device disclosed in U.S. Pat. No. 6,459,127. The high voltage device is also a N-type metal oxide semiconductor (MOS) transistor. A gate 110 of the NMOS is formed on a P substrate 100. An N+ region 112 is a source of the NMOS and an N well 102 a drain of the NMOS. An N+ region 106 is a contact point for the drain. The gate 110 controls the electrical connection of N+ region 112 and the N well 102. The gate 110 is coupled to a ground line or a pre-driver according to circuit requirements.
The P substrate 100 is coupled to the ground line through the P+ region 116. The N+ region 112 is coupled to the ground line. The drain is coupled to a pad through the N+ region 106. Due to low dosage concentration, the junction between the N well 102 and P substrate 100 has a very high breakdown voltage, such that high voltage signal can be input from the pad into the N well 102 and does not cause junction breakdown.
The parasitic SCR comprises a P+ region 104, the N well 102, P substrate 100, and N+ region 112. P+ region 104 is located beside N+ region 106 and beyond the gate 110. The parasitic SCR is turned on when positive ESD voltage occurs in the pad and the P substrate 100 is grounded. In FIG. 2, a discharge path A while the SCR is turned on is shown as a dotted line. The majority of the ESD current flows from the P+ region 104, the N well 102, P substrate 100, and N+ region 112 to the ground line releasing ESD stress.